In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the "5 nm" process as the MOSFET technology node following the "7 nm" node. In 2020, Samsung and TSMC entered volume production of "5 nm" chips, manufactured for companies including Apple, Marvell, Huawei and Qualcomm.[1][2]
The term "5 nm" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors being five nanometers in size. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a "5 nm node is expected to have a contacted gate pitch of 51 nanometers and a tightest metal pitch of 30 nanometers".[3] However, in real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process.[4][5]
^Cutress, Dr Ian. "'Better Yield on 5nm than 7nm': TSMC Update on Defect Rates for N5". AnandTech. Archived from the original on 30 August 2020. Retrieved 28 August 2020.
^"Marvell and TSMC Collaborate to Deliver Data Infrastructure Portfolio on 5nm Technology". HPCwire. Archived from the original on 15 September 2020. Retrieved 28 August 2020.
^International Roadmap for Devices and Systems: 2021 Update: More Moore, IEEE, 2021, p. 7, archived from the original on 7 August 2022, retrieved 7 August 2022
^"TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". 10 September 2019. Archived from the original on 17 June 2020. Retrieved 20 April 2020.
^Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Archived from the original on 2 December 2020. Retrieved 20 April 2021.
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of 7 nmprocess. 5nm (options: FinFET (FF)). 4 nm (options: FinFET (FF)). risk production started in 2021, enhanced version of 5nmprocess. 3 nm (options:...
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reserved as link to the chipset. No integrated graphics. Fabrication process: TSMC 4 nm FinFET. v t e Core Complexes (CCX) × cores per CCX, or Zen 4 + Zen...
example, Intel's former 10 nmprocess actually has features (the tips of FinFET fins) with a width of 7 nm, so the Intel 10 nmprocess is similar in transistor...
image processor with improved computational photography capabilities. A14 is manufactured by TSMC on their first-generation 5nm fabrication process, N5...
production, targeting 5 nanometer (nm) and 3 nmprocess nodes. The EUV wavelengths that are used in EUVL are near 13.5 nanometers (nm), using a laser-pulsed...
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