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7 nm process information


Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
  • 020 µm – 1968
  • 010 µm – 1971
  • 006 µm – 1974
  • 003 µm – 1977
  •  1.5 µm – 1981
  • 001 µm – 1984
  • 800 nm – 1987
  • 600 nm – 1990
  • 350 nm – 1993
  • 250 nm – 1996
  • 180 nm – 1999
  • 130 nm – 2001
  • 090 nm – 2003
  • 065 nm – 2005
  • 045 nm – 2007
  • 032 nm – 2009
  • 028 nm – 2010
  • 022 nm – 2012
  • 014 nm – 2014
  • 010 nm – 2016
  • 007 nm – 2018
  • 005 nm – 2020
  • 003 nm – 2022
Future
  • 002 nm ~ 2024
  • Half-nodes
  • Density
  • CMOS
  • Device (multi-gate)
  • Moore's law
  • Transistor count
  • Semiconductor
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  • Nanoelectronics
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In semiconductor manufacturing, the "7 nm" process is a term for the MOSFET technology node following the "10 nm" node, defined by the International Roadmap for Devices and Systems (IRDS), which was preceded by the International Technology Roadmap for Semiconductors (ITRS). It is based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology. As of 2021, the IRDS Lithography standard gives a table of dimensions for "7 nm",[1] with a few given below:

Calculated Value nm
minimum half pitch (DRAM, MPU metal) 18
minimum half pitch (Flash, MPU fin, LGAA) 15
minimum required OL (DRAM, Flash, MPU) 3.6
Gate pitch 54
Gate length 20

The 2021 IRDS Lithography standard is a backward-facing document, as the first volume production of a "7 nm" branded process, as Taiwan Semiconductor Manufacturing Company (TSMC) began production of 256 Mbit SRAM memory chips using a "7 nm" process called N7 in June 2016,[2] before Samsung began mass production of their "7 nm" process called 7LPP devices in 2018.[3] These process nodes had the same approximate transistor density as Intel's "10 nm Enhanced Superfin" node, later rebranded "Intel 7."[4]

Since at least 1997, the length scale of a process node has not referred to any particular dimension on the integrated circuits, such as gate length, metal pitch, or gate pitch, as new lithography processes no longer uniformly shrank all features on a chip. By the late 2010s, the length scale had become a commercial name[5] that indicated a new generation of process technologies, without any relation to physical properties.[6][7][8] Previous ITRS and IRDS standards had insufficient guidance on process node naming conventions to address the widely varying dimensions on a chip, leading to divergence between how foundries branded their lithography and the actual dimensions their process nodes achieved.

The first mainstream "7 nm" mobile processor intended for mass market use, the Apple A12 Bionic, was released at Apple's September 2018 event.[9] Although Huawei announced its own "7 nm" processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips were manufactured by TSMC.[10]

In 2019,[11] AMD released their "Rome" (EPYC 2) processors for servers and datacenters, which are based on TSMC's N7 node[12] and feature up to 64 cores and 128 threads. They also released their "Matisse" consumer desktop processors with up to 16 cores and 32 threads. However, the I/O die on the Rome multi-chip module (MCM) is fabricated with the GlobalFoundries' 14 nm (14HP) process, while the Matisse's I/O die uses the GlobalFoundries' "12 nm" (12LP+) process. The Radeon RX 5000 series is also based on TSMC's N7 process.

  1. ^ "International Roadmap for Devices and Systems 2021 Update: Lithography" (PDF). International Roadmap for Devices and Systems. April 7, 2024.
  2. ^ Cite error: The named reference tsmc was invoked but never defined (see the help page).
  3. ^ Chen, Monica; Shen, Jessie (June 22, 2018). "TSMC ramping up 7nm chip production". DigiTimes. Retrieved September 17, 2022.
  4. ^ Subramaniam, Vaidyanathan (July 27, 2021). "Intel details new process innovations and node names, Alder Lake 10 nm Enhanced SuperFin is now Intel 7; Intel 20A is the 2 nm process for 2024". Notebook Check.
  5. ^ Morris, Kevin (July 23, 2020). "No More Nanometers: It's Time for New Node Naming". Electronic Engineering Journal. Retrieved September 17, 2022.
  6. ^ Shukla, Priyank. "A Brief History of Process Node Evolution". Design-Reuse. Retrieved July 9, 2019.
  7. ^ Hruska, Joel (June 23, 2014). "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists…". ExtremeTech. Retrieved September 17, 2022.
  8. ^ Pirzada, Usman (September 16, 2016). "Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". Wccftech. Retrieved September 17, 2022.
  9. ^ Shankland, Stephen (September 12, 2018). "Apple's A12 Bionic CPU for the new iPhone XS is ahead of the industry moving to 7nm chip manufacturing tech". CNET. Retrieved September 16, 2018.
  10. ^ Summers, N. (September 12, 2018). "Apple's A12 Bionic is the first 7-nanometer smartphone chip". Engadget. Retrieved September 20, 2018.
  11. ^ "AMD Launches Epyc Rome, First 7nm CPU". August 8, 2019.
  12. ^ Smith, Ryan (July 26, 2018). "AMD "Rome" EPYC CPUs to Be Fabbed By TSMC". AnandTech. Retrieved June 18, 2019.

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