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3 nm process information


Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
  • 020 µm – 1968
  • 010 µm – 1971
  • 006 µm – 1974
  • 003 µm – 1977
  •  1.5 µm – 1981
  • 001 µm – 1984
  • 800 nm – 1987
  • 600 nm – 1990
  • 350 nm – 1993
  • 250 nm – 1996
  • 180 nm – 1999
  • 130 nm – 2001
  • 090 nm – 2003
  • 065 nm – 2005
  • 045 nm – 2007
  • 032 nm – 2009
  • 028 nm – 2010
  • 022 nm – 2012
  • 014 nm – 2014
  • 010 nm – 2016
  • 007 nm – 2018
  • 005 nm – 2020
  • 003 nm – 2022
Future
  • 002 nm ~ 2024
  • Half-nodes
  • Density
  • CMOS
  • Device (multi-gate)
  • Moore's law
  • Transistor count
  • Semiconductor
  • Industry
  • Nanoelectronics
  • v
  • t
  • e

In semiconductor manufacturing, the "3 nm" process is the next die shrink after the "5 nm" MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. South Korean chipmaker Samsung started shipping its "3 nm" gate all around (GAA) process, named "3GAA", in mid-2022.[1][2] On 29 December 2022, Taiwanese chip manufacturer TSMC announced that volume production using its "3 nm" semiconductor node ("N3") was under way with good yields.[3] An enhanced "3 nm" chip process called "N3E" may have started production in 2023.[4] American manufacturer Intel planned to start 3 nm production in 2023.[5][6][7]

Samsung's "3 nm" process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's "3 nm" process still uses FinFET (fin field-effect transistor) technology,[8] despite TSMC developing GAAFET transistors.[9] Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor).[10] Intel's process (dubbed "Intel 3", without the "nm" suffix) will use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography, and power and area improvement.[11]

Projected node properties according to International Roadmap for Devices and Systems (2021)[12]
Node name Gate pitch Metal pitch Year
"5 nm" 51 nm 30 nm 2020
"3 nm" 48 nm 24 nm 2022
"2.1 nm" 45 nm 20 nm 2024?

The term "3 nanometer" has no direct relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a "3 nm" node is expected to have a contacted gate pitch of 48 nanometers, and a tightest metal pitch of 24 nanometers.[12]

However, in real world commercial practice, "3 nm" is used primarily as a marketing term by individual microchip manufacturers (foundries) to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[13][14] There is no industry-wide agreement among different manufacturers about what numbers would define a "3 nm" node.[15] Typically the chip manufacturer refers to its own previous process node (in this case the "5 nm" node) for comparison. For example, TSMC has stated that its "3 nm" FinFET chips will reduce power consumption by 25–30% at the same speed, increase speed by 10–15% at the same amount of power and increase transistor density by about 33% compared to its previous "5 nm" FinFET chips.[16][17] On the other hand, Samsung has stated that its "3 nm" process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous "5 nm" process.[18] EUV lithography faces new challenges at 3 nm which lead to the required use of multipatterning.[19]

  1. ^ Cite error: The named reference :0 was invoked but never defined (see the help page).
  2. ^ Cite error: The named reference samsung-3nm-gaa was invoked but never defined (see the help page).
  3. ^ Cite error: The named reference n3vm was invoked but never defined (see the help page).
  4. ^ Ramish Zafar (4 March 2022). "TSMC Exceeds 3nm Yield Expectations & Production Can Start Sooner Than Planned". wccftech.com. Archived from the original on 16 March 2022. Retrieved 19 March 2022.
  5. ^ Cite error: The named reference intel_rm_2025 was invoked but never defined (see the help page).
  6. ^ Gartenberg, Chaim (26 July 2021). "Intel has a new architecture roadmap and a plan to retake its chipmaking crown in 2025". The Verge. Archived from the original on 20 December 2021. Retrieved 22 December 2021.
  7. ^ "Intel Technology Roadmaps and Milestones". Intel. Archived from the original on 16 July 2022. Retrieved 17 February 2022.
  8. ^ Cutress, Dr Ian. "Where are my GAA-FETs? TSMC to Stay with FinFET for 3nm". AnandTech. Archived from the original on 2 September 2020. Retrieved 12 September 2020.
  9. ^ "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond – ExtremeTech". Extremetech.com. Archived from the original on 22 September 2020. Retrieved 12 September 2020.
  10. ^ "Samsung at foundry event talks about 3nm, MBCFET developments". Techxplore.com. Archived from the original on 22 November 2021. Retrieved 22 November 2021.
  11. ^ Patrick Moorhead (26 July 2021). "Intel Updates IDM 2.0 Strategy With New Node Naming And Transistor And Packaging Technologies". Forbes. Archived from the original on 18 October 2021. Retrieved 18 October 2021.
  12. ^ a b INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore, IEEE, 2021, p. 7, archived from the original on 7 August 2022, retrieved 7 August 2022
  13. ^ "TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". Pcgamesn.co. 10 September 2019. Archived from the original on 17 June 2020. Retrieved 20 April 2020.
  14. ^ Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Archived from the original on 2 December 2020. Retrieved 20 April 2021.
  15. ^ INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore, IEEE, 2021, p. 6, archived from the original on 7 August 2022, retrieved 7 August 2022, according to which "There is not yet a consensus on the node naming across different foundries and integrated device manufacturers (IDMs)".
  16. ^ Jason Cross (25 August 2020). "TSMC details its future 5nm and 3nm manufacturing processes—here's what it means for Apple silicon". Macworld. Archived from the original on 20 April 2021. Retrieved 20 April 2021.
  17. ^ Anton Shilov (31 August 2020). "The future of leading-edge chips according to TSMC: 5nm, 4nm, 3nm and beyond". Techradar.com. Archived from the original on 20 April 2021. Retrieved 20 April 2021.
  18. ^ "Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture". 30 June 2022. Archived from the original on 8 July 2022. Retrieved 8 July 2022.
  19. ^ Chen, Frederick (17 July 2022). "EUV's Pupil Fill and Resist Limitations at 3nm". LinkedIn. Archived from the original on 29 July 2022.

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