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Physical Address Extension information


In computing, Physical Address Extension (PAE), sometimes referred to as Page Address Extension,[1] is a memory management feature for the x86 architecture. PAE was first introduced by Intel in the Pentium Pro, and later by AMD in the Athlon processor.[2] It defines a page table hierarchy of three levels (instead of two), with table entries of 64 bits each instead of 32, allowing these CPUs to directly access a physical address space larger than 4 gigabytes (232 bytes).

The page table structure used by x86-64 CPUs when operating in long mode further extends the page table hierarchy to four or more levels, extending the virtual address space, and uses additional physical address bits at all levels of the page table, extending the physical address space. It also uses the topmost bit of the 64-bit page table entry as a no-execute or "NX" bit, indicating that code cannot be executed from the associated page. The NX feature is also available in protected mode when these CPUs are running a 32-bit operating system, provided that the operating system enables PAE.

  1. ^ Dual-Core Intel® Xeon® Processor 2.80 GHz Specification Update (PDF). Intel Corporation. October 2006. p. 18.
  2. ^ "Appendix E". AMD Athlon™ Processor x86 Code Optimization Guide (PDF) (Revision K ed.). AMD, Inc. February 2002. p. 250. Retrieved 2017-04-13. A 2-bit index consisting of PCD and PWT bits of the page table entry is used to select one of four PAT register fields when PAE (page address extensions) is enabled, or when the PDE doesn't describe a large page.

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Physical Address Extension

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In computing, Physical Address Extension (PAE), sometimes referred to as Page Address Extension, is a memory management feature for the x86 architecture...

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ARM architecture family

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to as XN, for eXecute Never. The Large Physical Address Extension (LPAE), which extends the physical address size from 32 bits to 40 bits, was added...

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PCI hole

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Pentium Pro, known as Physical Address Extension (PAE), allows certain 32-bit operating systems to access up to 36-bit memory addresses, even though individual...

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3 GB barrier

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certain versions of Windows Server and macOS that allow use of Physical Address Extension (PAE) mode on x86 to access more than 4 GiB of RAM. Whatever the...

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Memory address

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Physical Address Extensions (PAE) which support mapping 36-bit physical addresses to 32-bit virtual addresses. Many early processors held 2 addresses...

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X86

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1978 as a fully 16-bit extension of Intel's 8-bit 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be...

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AArch64

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virtual addresses based on the existing Large Physical Address Extension (LPAE), which was designed to be easily extended to 64-bit. Extension: Data gathering...

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2 GB limit

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of Physical Address Extension (PAE) can overcome this barrier by extending the addresses used to represent mappings between virtual and physical memory...

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Address Windowing Extensions

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Memory privilege to use AWE. On 32-bit systems, AWE depends on Physical Address Extension support when reserving memory above 4 GB. AWE was first introduced...

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Memory paging

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n-bit addressing may have 2n addressable units of RAM installed. An example is a 32-bit x86 processor with 4 GB and without Physical Address Extension (PAE)...

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RAM limit

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addressing, which resulted in total addressable space of 64 gigabytes, but it requires that the operating system support Physical Address Extension....

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Direct memory access

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the Physical Address Extension (PAE), a 36-bit addressing mode. In such a case, a device using DMA with a 32-bit address bus is unable to address memory...

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PAE

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output file format for errors of protein structure prediction Physical Address Extension, an x86 computer processor feature for accessing more than 4 gigabytes...

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Out of memory

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a larger address space than is available at the process level. Some high-end 32-bit systems (such as those with Physical Address Extension enabled) come...

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Multiple buffering

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specific addressing requirements of a device (esp. 32-bit devices on systems with wider addressing provided via Physical Address Extension). DOS and...

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Flat memory model

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using Physical Address Extension (PAE) in Pentium Pro and later x86 CPUs to support 36-bit physical addresses to address more than 4GB of physical memory...

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X86 memory segmentation

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the 386, but can be larger on newer processors which support Physical Address Extension. The 80386 also introduced two new general-purpose data segment...

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MAC address

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burned-in address, or as an Ethernet hardware address, hardware address, or physical address. Each address can be stored in the interface hardware, such...

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Memory management unit

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known as virtual memory addresses, into physical addresses in main memory. In modern systems, programs generally have addresses that access the theoretical...

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Page Size Extension

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page. This allows a large page to be located in 36-bit address space. If Physical Address Extension (PAE) is used, the size of large pages is reduced from...

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CPUID

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A value of 0 indicates that the "Guest Physical Address Size" is the same as the "Number Of Physical Address Bits", specified in EAX[7:0]. This leaf...

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CentOS

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IA-32 in all variants, not supported since CentOS 7 IA-32 without Physical Address Extension (PAE), not supported since CentOS 6 IA-64 (Intel Itanium architecture)...

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List of Intel CPU microarchitectures

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avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)". Pentium M: updated version of Pentium III's...

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NTLDR

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is triggering a failure. /NOPAE – Forces Ntldr to load the non-Physical Address Extension (PAE) version of the Windows kernel, even if the system is detected...

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