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Interrupt descriptor table information


The interrupt descriptor table (IDT) is a data structure used by the x86 architecture to implement an interrupt vector table. The IDT is used by the processor to determine the correct response to interrupts and exceptions.

The details in the description below apply specifically to the x86 architecture. Other architectures have similar data structures, but may behave differently.

Use of the IDT is triggered by three types of events: hardware interrupts, software interrupts, and processor exceptions, which together are referred to as interrupts. The IDT consists of 256 interrupt vectors–the first 32 (0–31 or 0x00–0x1F) of which are used for processor exceptions.[1]

  1. ^ "Exceptions - OSDev Wiki". wiki.osdev.org. Retrieved 2021-04-17.

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The interrupt descriptor table (IDT) is a data structure used by the x86 architecture to implement an interrupt vector table. The IDT is used by the processor...

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affected by an interrupt, it looks up the interrupt handler in the interrupt vector table, and transfers control to it. Interrupt descriptor table (x86 Architecture...

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The Global Descriptor Table (GDT) is a data structure used by Intel x86-family processors starting with the 80286 in order to define the characteristics...

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Task state segment

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the Interrupt Stack Table (IST), which also resides in the TSS and contains logical (segment+offset) stack pointers. If an interrupt descriptor table specifies...

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BIOS interrupt call

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compatibility problems of BIOS and protected mode. DOS interrupt call Interrupt descriptor table Ralf Brown's Interrupt List Not all computers with BIOS are IBM PC...

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General protection fault

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accessing descriptor tables such as the Global Descriptor Table (GDT), the Interrupt descriptor table (IDT) and the Local Descriptor Table (LDT). Segment...

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Context switch

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JMP instruction targeted at a TSS descriptor in the global descriptor table. It can occur implicitly when an interrupt or exception is triggered if there's...

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Pentium F00F bug

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the table of interrupt descriptors, which normally resides on a single memory page, is instead split over two pages such that the descriptors for the...

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IDT

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transducer, a sensor and transmitter for a surface acoustic wave Interrupt descriptor table, a memory structure of x86 microprocessors Insulation-displacement...

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Null pointer

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code written in C for 16-bit real-mode x86 devices may write the interrupt descriptor table (IDT) at physical address 0 of the machine by dereferencing a...

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Triple fault

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device driver which writes over the interrupt descriptor table (IDT). If the IDT is corrupted, when the next interrupt happens, the processor will be unable...

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X86 virtualization

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get the descriptors back from the processor. Shadow descriptor tables must therefore be used to track changes made to the descriptor tables by the guest...

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LOADALL

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processor state that are normally outside of the IA-32 API scope, like descriptor cache registers. The LOADALL for 286 processors is encoded 0Fh 05h, while...

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X86 instruction listings

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descriptors used by the LGDT, LIDT, SGDT and SIDT instructions consist of a 2-part data structure. The first part is a 16-bit value, specifying table...

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Kernel Patch Protection

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include: Modifying system service descriptor tables Modifying the interrupt descriptor table Modifying the global descriptor table Using kernel stacks not allocated...

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ISO 9660

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The rest begins with a volume descriptor set (a header block which describes the subsequent layout) and then the path tables, directories and files on the...

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X86 memory segmentation

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reads the 64-bit segment descriptor structure from either the Global Descriptor Table when TI=0 or the Local Descriptor Table when TI=1. It then performs...

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Unisys 2200 Series system architecture

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via interrupts. The next part of the virtual address is the BDI or Bank Descriptor Index. The Level field selected a particular bank descriptor table base...

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Memory management unit

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point to the block in memory (another pbit). This makes descriptors equivalent to a page-table entry in an MMU system. System performance can be monitored...

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Protected mode

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Protected mode may only be entered after the system software sets up one descriptor table and enables the Protection Enable (PE) bit in the control register...

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X86

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into a descriptor table that is stored in memory. There are two such tables, the Global Descriptor Table (GDT) and the Local Descriptor Table (LDT), each...

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Cisco IOS

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processor), which performs the actual packet forwarding function. An Interface Descriptor Block, or simply IDB, is a portion of memory or Cisco IOS internal data...

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Extended memory

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makes this memory available through the Global Descriptor Table (GDT) and one or more Local Descriptor Tables (LDTs). The memory is "protected" in the sense...

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Design of the FAT file system

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Versions of DOS before 3.2 totally or partially relied on the media descriptor byte in the BPB or the FAT ID byte in cluster 0 of the first FAT in order...

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X86 assembly language

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of an address, it uses an interrupt vector, an index into a table of interrupt handler addresses. Typically, the interrupt handler saves all other CPU...

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Burroughs Large Systems

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program, the T field of an Operand Call or Descriptor Call syllable is relative to the Program Reference Table (PRT). For subroutines, the type of addressing...

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