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Low Pin Count information


Low Pin Count
Low Pin Count
Year created1998
Created byIntel
SupersedesIndustry Standard Architecture
Superseded byEnhanced Serial Peripheral Interface Bus (2016)
Width in bits4
Speed33 MHz
StyleParallel
Hotplugging interfaceno
External interfaceno
Low Pin Count
Low Pin Count interface Winbond chip
Trusted Platform Module installed on a motherboard, and using the LPC bus

The Low Pin Count (LPC) bus is a computer bus used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the BIOS ROM (BIOS ROM was moved to the Serial Peripheral Interface (SPI) bus in 2006[1]), "legacy" I/O devices (integrated into Super I/O, Embedded Controller, CPLD, and/or IPMI chip), and Trusted Platform Module (TPM).[2] "Legacy" I/O devices usually include serial and parallel ports, PS/2 keyboard, PS/2 mouse, and floppy disk controller.

Most PC motherboards with an LPC bus have either a Platform Controller Hub (PCH) or a southbridge chip, which acts as the host and controls the LPC bus. All other devices connected to the physical wires of the LPC bus are peripherals.

  1. ^ https://images.slideplayer.com/26/8671671/slides/slide_5.jpg [bare URL image file]
  2. ^ Johannes Winter (2011). "A Hijacker's Guide to the LPC bus". tugraz.at. Retrieved 2013-12-19.

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