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Undocumented CPU instruction that has an effect
Machine code
General concepts
Instruction set
Opcode
Illegal opcode
Opcode table
Operand
Instructions
NOP
Branch
Indirect branch
Repeat instruction
Execute instruction
v
t
e
An illegal opcode, also called an unimplemented operation,[1]unintended opcode[2] or undocumented instruction, is an instruction to a CPU that is not mentioned in any official documentation released by the CPU's designer or manufacturer, which nevertheless has an effect. Illegal opcodes were common on older CPUs designed during the 1970s, such as the MOS Technology 6502, Intel 8086, and the Zilog Z80. On these older processors, many exist as a side effect of the wiring of transistors in the CPU, and usually combine functions of the CPU that were not intended to be combined. On old and modern processors, there are also instructions intentionally included in the processor by the manufacturer, but that are not documented in any official specification.
The effect of many illegal opcodes, on many processors, is just a trap to an error handler. However, some processors that trap for most illegal opcodes do not do so for some illegal opcodes, and some other processors do not check for illegal opcodes, and, instead, perform an undocumented operation.
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An illegalopcode, also called an unimplemented operation, unintended opcode or undocumented instruction, is an instruction to a CPU that is not mentioned...
In computing, an opcode (abbreviated from operation code, also known as instruction machine code, instruction code, instruction syllable, instruction parcel...
An opcode table (also called an opcode matrix) is a visual representation of all opcodes in an instruction set. It is arranged such that each axis of...
classify some exceptions not related to access violations, such as illegalopcode exceptions, as general protection faults, even though they have nothing...
instructions. On the processing architecture, a given instruction may specify: opcode (the instruction to be performed) e.g. add, copy, test any explicit operands:...
TOS to zero and restart the operation. … Illegalopcodes that are instruction holes in the MMX instruction opcode map are defined to generate a one uop assist...
software (with optimised ARM/ThumbEE JVM code), or treated as an invalid/illegalopcode. The third case will cause a branch to an ARM exception mode, as will...
exceptional condition (e.g., division by zero, invalid memory access, illegalopcode), although the term exception is more common for this. x86 divides interrupts...
are several other undocumented instructions as well. Undocumented or illegalopcodes are not detected by the Z80 and have various effects, some of which...
Macintosh operating system executes system calls using that processor's illegalopcode exception handling mechanism. Motorola specified that instructions beginning...
unlicensed clone of the Zilog Z80 microprocessor, also supporting illegalopcodes and bugs, except for very minor differences like not setting the CY...
4-687. Stecklina, Julian (2019-02-08). "Fingerprinting x86 CPUs using IllegalOpcodes". x86.lol. Archived from the original on 15 Dec 2023. Retrieved 2023-12-15...
compare and exchange of 8 bytes in register EAX). The bug also applies to opcodes ending in C9 through CF, which specify register operands other than EAX...
those that did not follow Apple programming guidelines and rules, used illegalopcodes that were no longer available in the new CMOS-based CPU, or used the...
on the model, the control board might also contain hardware to flag illegalopcodes or memory accesses or to act as an internal logic analyzer. Memory...
the 6502, but was incompatible with programs that used deprecated illegalopcodes of the 6502. (Apple stated that the Apple IIc was compatible with 90–95%...
RAX and RDX. Its opcode is 0F 31. Pentium competitors such as the Cyrix 6x86 did not always have a TSC and may consider RDTSC an illegal instruction. Cyrix...