Process of scaling down the size of semiconductor devices
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Semiconductor device fabrication
MOSFET scaling (process nodes)
020 µm – 1968
010 µm – 1971
006 µm – 1974
003 µm – 1977
1.5 µm – 1981
001 µm – 1984
800 nm – 1987
600 nm – 1990
350 nm – 1993
250 nm – 1996
180 nm – 1999
130 nm – 2001
090 nm – 2003
065 nm – 2005
045 nm – 2007
032 nm – 2009
028 nm – 2010
022 nm – 2012
014 nm – 2014
010 nm – 2016
007 nm – 2018
005 nm – 2020
003 nm – 2022
Future
002 nm ~ 2024
Half-nodes
Density
CMOS
Device (multi-gate)
Moore's law
Transistor count
Semiconductor
Industry
Nanoelectronics
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The term die shrink (sometimes optical shrink or process shrink) refers to the scaling of metal–oxide–semiconductor (MOS) devices. The act of shrinking a die creates a somewhat identical circuit using a more advanced fabrication process, usually involving an advance of lithographic nodes. This reduces overall costs for a chip company, as the absence of major architectural changes to the processor lowers research and development costs while at the same time allowing more processor dies to be manufactured on the same piece of silicon wafer, resulting in less cost per product sold.
Die shrinks are the key to lower prices and higher performance at semiconductor companies such as Samsung, Intel, TSMC, and SK Hynix, and fabless manufacturers such as AMD (including the former ATI), NVIDIA and MediaTek.
dieshrink (sometimes optical shrink or process shrink) refers to the scaling of metal–oxide–semiconductor (MOS) devices. The act of shrinking a die creates...
the memory controller into the CPU die. Added important powerful new instructions, SSE4.2. Westmere: 32 nm shrink of the Nehalem microarchitecture with...
In semiconductor manufacturing, the "3 nm" process is the next dieshrink after the "5 nm" MOSFET (metal–oxide–semiconductor field-effect transistor) technology...
continued its tick-tock model of a microarchitecture change followed by a dieshrink until the 6th-generation Core family based on the Skylake microarchitecture...
process is a half-node semiconductor manufacturing process based on a dieshrink of the "32 nm" lithography process. It appeared in production in 2010...
disturbing Moore's law. The 20-nanometre node is an intermediate half-node dieshrink based on the 22-nanometre process. TSMC began mass production of 20 nm...
is the next MOSFET (metal–oxide–semiconductor field-effect transistor) dieshrink after the "3 nm" process node. The term "2 nanometer" or alternatively...
Skymont) is Intel's codename for the 10-nanometer dieshrink of the Kaby Lake microarchitecture. As a dieshrink, Cannon Lake is a new process in Intel's...
soldered contact with the die and IHS (Integrated Heat Spreader), while Intel's subsequent generation Ivy Bridge uses a 22 nm dieshrink and a TIM (Thermal Interface...
Family 15h (3rd-gen) – third-generation Bulldozer (Second optimisation and dieshrink to 28 nm). CPUID model numbers are 30h-3Fh. AMD Excavator Family 15h (4th-gen)...
the desktop Clarkdale processor; both use dual-core dies based on the Westmere 32 nm dieshrink of the Nehalem microarchitecture, and have integrated...
technology 3.0–3.6 GHz (model numbers 6x1) Introduced January 16, 2006 Dieshrink of Prescott-2M Same features as Prescott-2M Family 15 Model 4 Dual-core...
processor continued an emphasis on minimizing power consumption with the next dieshrink to a mixed 130/150 nm process. "Ezra" (C5C) and "Ezra-T" (C5N) were only...
thirty-two nanometers. The "28 nm" node is an intermediate half-node dieshrink based on the "32 nm" process. The "32 nm" process was superseded by commercial...
ERMIC still with the MME name and logo, Thesys under its new name. A dieshrink chip with the marking U880/6 had been developed in 1990 and went into...
announced in 1H14. According to the Tick–tock model Airmont is the 14 nm dieshrink of Silvermont, launched in early 2015 and first seen in the Atom x7-Z8700...
minimum sizes and tighter spacing. In some cases, this allows a simple dieshrink of a currently produced chip design to reduce costs, improve performance...
series), for both the base and digital versions of the PS5, which used a dieshrink of the original SoC. This lowered the power draw of the SoC and Sony redesigned...
process permitting 180-nanometer processor production. The accompanying die-shrink resulted in lower power consumption, permitting AMD to increase Athlon...
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