This article needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. Find sources: "Delay insensitive circuit" – news · newspapers · books · scholar · JSTOR(July 2009) (Learn how and when to remove this message)
A delay-insensitive circuit is a type of asynchronous circuit which performs a digital logic operation often within a computing processor chip. Instead of using clock signals or other global control signals, the sequencing of computation in delay-insensitive circuit is determined by the data flow.
Data flows from one circuit element to another using "handshakes", or sequences of voltage transitions to indicate readiness to receive data, or readiness to offer data. Typically, inputs of a circuit module will indicate their readiness to receive, which will be "acknowledged" by the connected output by sending data (encoded in such a way that the receiver can detect the validity directly[1]), and once that data has been safely received, the receiver will explicitly acknowledge it, allowing the sender to remove the data, thus completing the handshake, and allowing another datum to be transmitted.
In a delay-insensitive circuit, there is therefore no need to provide a clock signal to determine a starting time for a computation. Instead, the arrival of data to the input of a sub-circuit triggers the computation to start. Consequently, the next computation can be initiated immediately when the result of the first computation is completed.
The main advantage of such circuits is their ability to optimize processing of activities that can take arbitrary periods of time depending on the data or requested function. An example of a process with a variable time for completion would be mathematical division or recovery of data where such data might be in a cache.
The Delay-Insensitive (DI) class is the most robust of all asynchronous circuit delay models. It makes no assumptions on the delay of wires or gates. In this model all transitions on gates or wires must be acknowledged before transitioning again. This condition stops unseen transitions from occurring. In DI circuits any transition on an input to a gate must be seen on the output of the gate before a subsequent transition on that input is allowed to happen. This forces some input states or sequences to become illegal. For example OR gates must never go into the state where both inputs are one, as the entry and exit from this state will not be seen on the output of the gate. Although this model is very robust, no practical circuits are possible due to the lack of expressible conditionals in DI circuits.[2] Instead the Quasi-Delay-Insensitive model is the smallest compromise model yet capable of generating useful computing circuits. For this reason circuits are often incorrectly referred to as Delay-Insensitive when they are Quasi Delay-Insensitive.
^Verhoeff, Tom (January 1987). "Delay-Insensitive Codes--An Overview".
^Martin, Alain. "The Limitations to Delay-Insensitivity in Asynchronous Circuits" (PDF).
and 20 Related for: Delay insensitive circuit information
A delay-insensitivecircuit is a type of asynchronous circuit which performs a digital logic operation often within a computing processor chip. Instead...
indicated by a locally generated delay model – to delay-insensitive design – where arbitrary delays through circuit elements can be accommodated. The...
commands are suitable for quasi-delay-insensitivecircuit design because the repetition allows arbitrary relative delays for the selection of different...
much more useful, are quasi-delay-insensitivecircuits (also known as speed-independent circuits), such as delay-insensitive minterm synthesis, which operate...
unidirectional error detecting codes, Berger codes can also be used in delay-insensitivecircuits. As stated above, Berger codes detect any number of unidirectional...
amplifier applications. A non-ideal operational amplifier's equivalent circuit has a finite input impedance, a non-zero output impedance, and a finite...
more recent examples for qubits used in circuit QED are so called transmon qubits (more charge noise insensitive compared to the Cooper-pair box) and flux...
must be a delay before the anode can be positively biased and retain the thyristor in the off-state. This minimum delay is called the circuit commutated...
Devoret, M. H.; Girvin, S. M.; Schoelkopf, R. J. (2007-10-12). "Charge-insensitive qubit design derived from the Cooper pair box". Physical Review A. 76...
Hexanitrostilbene: Used in detonators, linear shaped charges, and bulk explosives. Insensitive to stimuli other than explosion. Thermally stable. Vacuum stable. Used...
sensitive device used to provoke a larger, more powerful but relatively insensitive secondary explosive of an explosive device used in commercial mining...
device intended to protect electrical devices in alternating current (AC) circuits from voltage spikes with very short duration measured in microseconds,...
will interfere constructively if delayed by 180 degrees forming positive feedback. In these cases, the feedback circuit can be stabilized by means of frequency...
distrusts a wounded young deer, Ryu retorts that there's nobody more insensitive than Joe. Meanwhile, Jinpei discovers Katse and corners him, but is in...
his place in history—not as a brilliant jurist, but as among the most insensitive Irons, Peter (2006). A People's History of the Supreme Court: The Men...
voiding is needed to create a temperature-sensitive propagation delay. Sometimes, circuit tolerances can make erratic behaviour difficult to trace; for...
acceptable for class 2 capacitors, which are primarily used in accuracy-insensitive, low-cost applications such as power supplies. NME still sees use in...
environments e.g. classrooms, shopping malls Poor listening skills Insensitivity to tone of voice or other nuances of speech Acquired brain injury History...
"NBC apologizes to Korean people after correspondent's 'ignorant, 'insensitive' comment". MSN. Archived from the original on February 11, 2018. Retrieved...
Global Information