Electronics verification methodology for analog circuits
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Analog verification is a methodology for performing functional verification on analog, mixed-signal and RF integrated circuits and systems on chip.[1] Discussion of analog verification began in 2005 when it started to become recognized that the analog portion of large mixed-signal chips had become so complex that a significant and ever-increasing number of these chips were being designed with functional errors in the analog portion that prevented them from operating correctly.
^Henry Chang and Ken Kundert. Verification of Complex Analog and RF IC Designs Archived July 10, 2020, at the Wayback Machine. Proceedings of the IEEE, February 2007.
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