IEEE 1800-2023
/ 6 December 2023; 5 months ago (2023-12-06)
Typing discipline
Static, weak
Filename extensions
.v, .vh
Website
https://ieeexplore.ieee.org/document/10458102
Dialects
Verilog-AMS
Influenced by
Pascal, Ada, C, Fortran
Influenced
SystemVerilog
Programmable Logic/Verilog at Wikibooks
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.[citation needed] It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits.[1] In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog has been officially part of the SystemVerilog language. The current version is IEEE standard 1800-2023.[2]
^Nielsen AA, Der BS, Shin J, Vaidyanathan P, Paralanov V, Strychalski EA, Ross D, Densmore D, Voigt CA (2016). "Genetic circuit design automation". Science. 352 (6281): aac7341. doi:10.1126/science.aac7341. PMID 27034378.
^Cite error: The named reference IEEE2023 was invoked but never defined (see the help page).
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design...
and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008, Verilog is now part of the same IEEE standard....
Icarus Verilog is an implementation of the Verilog hardware description language compiler that generates netlists in the desired format (EDIF) and a simulator...
written in one of the hardware description languages, such as VHDL, Verilog, SystemVerilog. This page is intended to list current and historical HDL simulators...
It allows behavioral Verilog code to invoke C functions, and C functions to invoke standard Verilog system tasks. The Verilog Procedural Interface is...
term rewriting system (TRS). It comes with a SystemVerilog frontend. BSV is compiled to the Verilog RTL design files. BSV releases are shipped with the...
limited experimental support for Verilog and VHDL. Electronics portal List of HDL simulators for VHDL, Verilog, SystemVerilog, ... Espresso heuristic logic...
In integrated circuit design, VerilogCSP is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications...
circuit. There are two major hardware description languages: VHDL and Verilog. There are different types of description in them: "dataflow, behavioral...
SystemVerilog DPI (Direct Programming Interface) is an interface which can be used to interface SystemVerilog with foreign languages. These foreign languages...
"Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at...
computer code into a hardware description language (HDL) such as VHDL or Verilog. The converted code can then be synthesized and translated into a hardware...
was founded from the merger of Open Verilog International (OVI) and VHDL International, the developers of Verilog and VHDL respectively. Both were originally...
Graphics,) for simulation of hardware description languages such as VHDL, Verilog and SystemC, and includes a built-in C debugger. ModelSim can be used independently...
one of the mainstream hardware description languages (HDL) like VHDL or Verilog. Other tools instead operate at a higher level of abstraction and allow...
Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++...
circuit. Pure digital simulations are also supported using VHDL and/or Verilog. Only a small set of digital devices like flip flops and logic gates can...
known for having developed the PODEM Automatic test pattern generation and Verilog hardware description language. In 1970 Goel graduated as an electrical...
VHDL and Verilog code from a MyHDL design. The ability to generate a testbench (Conversion of test benches) with test vectors in VHDL or Verilog, based...
tools. The standard, four-value VCD format was defined along with the Verilog hardware description language by the IEEE Standard 1364-1995 in 1996. An...
Global Information