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Latency oriented processor architecture information


Latency oriented processor architecture is the microarchitecture of a microprocessor designed to serve a serial computing thread with a low latency. This is typical of most central processing units (CPU) being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to even a few hundred cycles in some cases.[1][page needed] Latency oriented processor architectures are the opposite of throughput-oriented processors which concern themselves more with the total throughput of the system, rather than the service latencies for all individual threads that they work on.[2][page needed][3]

  1. ^ John Paul Shen; Mikko H. Lipasti (2013). Modern Processor Design. McGraw-Hill Professional. ISBN 978-1478607830.
  2. ^ Yan Solihin (2016). Fundamentals of Parallel Multicore Architecture. Chapman & Hall/CRC Computational Science. ISBN 978-1482211184.
  3. ^ Michael Garland; David B. Kirk (2010). "Understanding Throughput-Oriented Architectures". Communications of the ACM. 53 (11): 58–66. doi:10.1145/1839676.1839694.

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