Computer processor interconnection technology first introduced in 2001
Not to be confused with Hyper-Threading, which is also sometimes abbreviated "HT".
Logo of the HyperTransport Consortium
HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link that was introduced on April 2, 2001.[1] The HyperTransport Consortium is in charge of promoting and developing HyperTransport technology.
HyperTransport is best known as the system bus architecture of AMD central processing units (CPUs) from Athlon 64 through AMD FX and the associated motherboard chipsets. HyperTransport has also been used by IBM and Apple for the Power Mac G5 machines, as well as a number of modern MIPS systems.
The current specification HTX 3.1 remained competitive for 2014 high-speed (2666 and 3200 MT/s or about 10.4 GB/s and 12.8 GB/s) DDR4 RAM and slower (around 1 GB/s [1] similar to high end PCIe SSDs ULLtraDIMM flash RAM) technology[clarification needed]—a wider range of RAM speeds on a common CPU bus than any Intel front-side bus. Intel technologies require each speed range of RAM to have its own interface, resulting in a more complex motherboard layout but with fewer bottlenecks. HTX 3.1 at 26 GB/s can serve as a unified bus for as many as four DDR4 sticks running at the fastest proposed speeds. Beyond that DDR4 RAM may require two or more HTX 3.1 buses diminishing its value as unified transport.
^"API NetWorks Accelerates Use of HyperTransport Technology With Launch of Industry's First HyperTransport Technology-to-PCI Bridge Chip". HyperTransport Consortium (Press release). April 2, 2001. Archived from the original on October 10, 2006.
HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel...
The HyperTransport Consortium is an industry consortium responsible for specifying and promoting the computer bus technology called HyperTransport. The...
CPUs communicate using the Direct Connect Architecture over high-speed HyperTransport links. Each CPU can access the main memory of another processor, transparent...
dual-channel architecture, doubling peak memory bandwidth, and the HyperTransport bus was increased in speed from 800 MHz to 1000 MHz. Socket 939 also...
Athlon 64, including an integrated (on-die) memory controller, the HyperTransport link, and AMD's "NX bit" feature. In the second half of 2005, AMD added...
64-bit single channel on-die DDR-400 memory controller, and an 800 MHz HyperTransport bus. Battery saving features, like PowerNow!, are central to the marketing...
allowing for modification of the CPU speed without changing the FSB or HyperTransport. On a non-black edition CPU, the multiplier is allowed to only be lowered...
PowerNow! Technology (Cool’n’Quiet Technology) HyperTransport Technology (not the same as Intel Hyper-Threading Technology) Processors with an "e" following...
include: HyperTransport – a high-bandwidth, low-latency system bus used in AMD's CPU and APU products Infinity Fabric – a derivative of HyperTransport used...
Improvements in system interconnect: HyperTransport retry support Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point...
Motherboards: One HyperTransport 3.x link between CPU with 2.2 GHz, two HT 2.x links with 1 GHz for I/O operations Socket Fr6 Three Hypertransport 3.x links with...
HyperTransport is used, running at 800 MHz for Semprons. The multipliers here apply to the 200 MHz system clock frequency, not the HyperTransport speed...
intermediate successor to socket AM2, which features split power planes, and HyperTransport 3.0. Socket AM2+ chips can plug into a socket AM2 motherboard (although...
SSE3 (revision E or later) instruction sets. It features one 16 bit HyperTransport link running up to 1000 MT/s. In regards to video expansion slots, Socket...
designed around a 64-bit ISA, added an integrated memory controller, HyperTransport communication fabric, L2 cache sizes up to 1 MB (1128 KB total cache)...
consumer market. Some features for Athlon 64 X2 processors include: Use of HyperTransport technology for I/O devices System Management Mode 32-bit compatibility...
extinct language of Anatolia ZIC3, a protein HyperTransport Expansion connector, part of the HyperTransport specification This disambiguation page lists...
lanes and 4 PCIe 1.1 for A-Link Express II solely in the Northbridge HyperTransport 3.0 with support for HTX slots and PCI Express 2.0 ATI CrossFire X AutoXpress...
dual-core PowerPC G5 configurations, which can communicate through its HyperTransport at half its internal clock speed. Each processor in the Power Mac G5...
support of AM3+ CPUs, AMD has validated the 9-Series chipset for use with HyperTransport 3.1 (up to 6.4 GT/s). They also worked with NVIDIA to bring SLI support...
the initialization of the CPU cores, chipset, main memory, and the HyperTransport controller. AGESA was open sourced in early 2011, aiming to aid in the...
Contacts 941 (Socket) 938 (CPU) FSB protocol HyperTransport 3.x FSB frequency 200 MHz System clock HyperTransport up to 2.6 GHz Processors Phenom II Athlon...
package, supporting both unbuffered or buffered DDR3 (with Socket G3MX), HyperTransport 3.0 and IOMMU, all of them forming the codenamed "Piranha" server platform...
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