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Intel Hub Architecture (IHA), also known as Accelerated Hub Architecture (AHA) was Intel's architecture for the 8xx family of chipsets,[1][2] starting in 1999 with the Intel 810. It uses a memory controller hub (MCH) that is connected to an I/O controller hub (ICH) via a 266 MB/s bus. The MCH chip supports memory and AGP (replaced by PCI Express in 9xx series chipsets), while the ICH chip provides connectivity for PCI (revision 2.2 before ICH5 series and revision 2.3 since ICH5 series), USB (version 1.1 before ICH4 series and version 2.0 since ICH4 series), sound (originally AC'97, Azalia added in ICH6 series), IDE hard disks (supplemented by Serial ATA since ICH5 series, fully replaced IDE since ICH8 series for desktops and ICH9 series for notebooks) and LAN (uncommonly activated on desktop motherboards and notebooks, usually independent LAN controller were placed instead of PHY chip).[citation needed]
Intel claimed that, because of the high-speed channel between the sections, the IHA was faster than the earlier northbridge/southbridge design,[3] which hooked all low-speed ports to the PCI bus. The IHA also optimized data transfer based on data type.[citation needed]
^Talukdar, Mrinal (2021-01-19). Dictionary of Computer & Information Technology. Prabhat Prakashan. p. 10. ISBN 978-93-5048-505-7.
^Das, Lyla B (2010). The X86 Microprocessors: Architecture And Programming (8086 To Pentium). Pearson Education India. p. 566. ISBN 978-81-317-3246-5.
^Sammes, Tony; Jenkinson, Brian (2007). "PC Hardware and Inside the Box". Forensic Computing. Springer Science+Business Media. pp. 75–101. doi:10.1007/978-1-84628-732-9_4. ISBN 978-1-84628-397-0. Retrieved 2022-09-23.
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