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In lower power systems, Hierarchical Value Cache refers to the hierarchical arrangement of Value Caches (VCs) in such a fashion that lower level VCs observe higher hit-rates, but undergo more switching activity on VC hits.
The organization is similar to Memory Hierarchy, where lower-level caches enjoy higher hit rates, but longer hit latencies. The architecture for Hierarchical Value Cache is mainly organized along two approaches: Hierarchical Unified Value Cache[1] (HUVC) and Hierarchical Combinational Value Cache (HCVC).[2]
^Lin, C.-H.; Yang, C.-L.; King, K.-J. "Proceedings of the 2006 International Symposium on Low Power Electronics and Design" (2006): 35–42. {{cite journal}}: Cite journal requires |journal= (help)
^Lin, C.-H.; Yang, C.-L.; King, K.-J. "Proceedings of the 2006 International Symposium on Low Power Electronics and Design" (2006): 35–42. {{cite journal}}: Cite journal requires |journal= (help)
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