Microprocessor designed by the Moscow Center of SPARC Technologies
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Elbrus 2000
General information
Launched
2007; 17 years ago (2007)
Designed by
Moscow Center of SPARC Technologies (MCST)
Common manufacturer(s)
TSMC
Performance
Max. CPU clock rate
300 MHz
Architecture and classification
Instruction set
Elbrus
Physical specifications
Cores
1
The Elbrus 2000 (or e2k; Russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.
It supports two instruction set architectures (ISA): Elbrus VLIW and Intel x86 (a complete, system-level implementation with a software dynamic binary translation virtual machine, similar to Transmeta Crusoe).
Due to its unique architecture, the Elbrus 2000 can execute 20 instructions per clock, so even with its modest clock speed it can compete with much faster clocked superscalar microprocessors when running in native VLIW mode.[1][2] For security reasons, the Elbrus 2000 architecture implements dynamic data type-checking during execution. In order to prevent unauthorized access, each pointer has additional type information that is verified when the associated data is accessed.[3]
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