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In computers it is typical to define rules relative to data transfers for optimizing the overall system considerations. One such consideration is to define coherency granules (CG) that relate to units of data that are stored in memory. These units generally have a close relationship to caches that may be used in the system. The Coherency Granule size typically corresponds to the cache line size in a computer system.[1]
The hardware is designed with the assumption that coherency granules will be the data packets that are typically transferred in a cache coherent system when accessing coherent data. The magnitude of the coherency granule is typically significantly greater than the bus size. For example, in current processing systems, the coherency granule is commonly 32 bytes, and the bus size is 8 bytes wide. In such a case, a data transfer of one coherency granule requires 4 cycles on the bus. The hardware is designed to optimize, for example by using burst techniques, the performance of such transfers. Thus a burst transfer of a coherency granule will take less time than two transfers each of a half of a coherency granule.[1]
As systems continue to get more and more complex, there has been a tendency to increase the size of coherency granules. As the size of coherency granules increases, there is thus more data per coherency granule. This can make it more complicated since more data must be dealt with for each operation that must maintain the requirements of the coherency associated with the data.
^ abComputer Architecture: A Quantitative Approach, John L. Hennessy, David A. Patterson, Elsevier, 2012
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