Efficient hardware implementation of a digital multiplier
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4 layer Wallace reduction of an 8x8 partial product matrix, using 15 half adders (two dots) and 38 full adders (three dots). The dots in each column are bits of equal weight.
A Wallace multiplier is a hardware implementation of a binary multiplier, a digital circuit that multiplies two integers. It uses a selection of full and half adders (the Wallace tree or Wallace reduction) to sum partial products in stages until two numbers are left. Wallace multipliers reduce as much as possible on each layer, whereas Dadda multipliers try to minimize the required number of gates by postponing the reduction to the upper layers.[1]
Wallace multipliers were devised by the Australian computer scientist Chris Wallace in 1964.[2]
The Wallace tree has three steps:
Multiply each bit of one of the arguments, by each bit of the other.
Reduce the number of partial products to two by layers of full and half adders.
Group the wires in two numbers, and add them with a conventional adder.[3]
Compared to naively adding partial products with regular adders, the benefit of the Wallace tree is its faster speed. It has reduction layers, but each layer has only propagation delay. A naive addition of partial products would require time.
As making the partial products is and the final addition is , the total multiplication is , not much slower than addition. From a complexity theoretic perspective, the Wallace tree algorithm puts multiplication in the class NC1.
The downside of the Wallace tree, compared to naive addition of partial products, is its much higher gate count.
These computations only consider gate delays and don't deal with wire delays, which can also be very substantial.
The Wallace tree can be also represented by a tree of 3/2 or 4/2 adders.
It is sometimes combined with Booth encoding.[4][5]
^Townsend, Whitney J.; Swartzlander, Earl E.; Abraham, Jacob A. (2003). Luk, Franklin T. (ed.). "A comparison of Dadda and Wallace multiplier delays". Advanced Signal Processing Algorithms, Architectures, and Implementations XIII. 5205: 552–560. Bibcode:2003SPIE.5205..552T. doi:10.1117/12.507012. ISSN 0277-786X. S2CID 121437680.
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