This article needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. Find sources: "Static timing analysis" – news · newspapers · books · scholar · JSTOR(December 2021) (Learn how and when to remove this message)
Static timing analysis (STA) is a simulation method of computing the expected timing of a synchronous digital circuit without requiring a simulation of the full circuit.
High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Measuring the ability of a circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. The speedup comes from the use of simplified timing models and by mostly ignoring logical interactions in circuits.[1] This has become a mainstay of design over the last few decades.
One of the earliest descriptions of a static timing approach was based on the Program Evaluation and Review Technique (PERT), in 1966.[2] More modern versions and algorithms appeared in the early 1980s.[3][4][5]
^Cortadella, Jordi (January 30, 2017). Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology (2nd ed.). Boca Raton: CRC Press. p. 134. ISBN 9781315215112.
^Kirkpatrick, TI & Clark, NR (1966). "PERT as an aid to logic design". IBM Journal of Research and Development. 10 (2). IBM Corp.: 135–141. doi:10.1147/rd.102.0135.
^McWilliams, T.M. (1980). "Verification of timing constraints on large digital systems" (PDF). Design Automation, 1980. 17th Conference on. IEEE. pp. 139–147.
^G. Martin; J. Berrie; T. Little; D. Mackay; J. McVean; D. Tomsett; L. Weston (1981). "An integrated LSI design aids system". Microelectronics Journal. 12 (4): 18–22. doi:10.1016/S0026-2692(81)80259-5.
^Hitchcock, R. and Smith, G.L. and Cheng, D.D. (1982). "Timing analysis of computer hardware". IBM Journal of Research and Development. 26 (1). IBM: 100–105. CiteSeerX 10.1.1.83.2093. doi:10.1147/rd.261.0100.{{cite journal}}: CS1 maint: multiple names: authors list (link)
and 23 Related for: Static timing analysis information
Statictiminganalysis (STA) is a simulation method of computing the expected timing of a synchronous digital circuit without requiring a simulation of...
Conventional statictiminganalysis (STA) has been a stock analysis algorithm for the design of digital circuits for a long time. However the increased...
Timinganalysis may refer to: Statictiminganalysis, a simulation method which computes the expected timing of a synchronous digital circuit Dynamic timing...
is a form of simulation that tests circuit timing in its functional context. Dynamic timing verification Statictiminganalysis Dynamic TimingAnalysis...
ensure functional equivalence at the logical level. Statictiminganalysis: analysis of the timing of a circuit in an input-independent manner, hence finding...
flows, and forms an efficient bridge between dynamic timinganalysis and statictiminganalysis. It was originally developed as an OVI standard, and later...
used in applications such as logic synthesis, delay calculation, statictiminganalysis, placement and routing, since it is simple to compute (especially...
care is needed in the design of the clock distribution networks. Statictiminganalysis is often used to determine the maximum safe operating speed. Nearly...
the US Statictiminganalysis, of a digital circuit Station (computer networking), in IEEE 802.11 (Wi-Fi) terminology Simultaneous thermal analysis, in thermal...
various purposes including circuit simulation, statictiminganalysis, signal integrity, power analysis and optimization, and logic to layout comparison...
tasks are properly carried out during logic simulation or with a statictiminganalysis tool. A key traditional distinction between an emulator and an FPGA...
simulation can provide some feedback regarding signal timing, it is not a replacement for statictiminganalysis. In cycle simulation, it is not possible to specify...
circuit (IC) design. This is in contrast to statictiminganalysis, which has a similar goal as dynamic timing verification except it does not require simulating...
design Physical timing closure Statictiminganalysis Asynchronous circuit Phy-TC.Com. This article is derived from the document Timing closure by Alessandro...
constraints and objectives. Every step in the IC design (such as statictiminganalysis, placement, routing, and so on) is already complex and often forms...
Anomaly Singapore Space and Technology Association Statistical StaticTimingAnalysis Stockholm Stads Tekniska Aftonskola This disambiguation page lists...
and route must deal with them correctly, and other tools such as statictiminganalysis and formal verification must understand these components. As power...
including delays, transitions, timing constraints, and pin capacitances. Variety generates statistical statictiminganalysis (SSTA) models for a number of...
reducing the timing margin. If the signals have been designed with enough timing margin, only the correct data will be received. Statictiminganalysis Cortadella...
extracted circuit netlist with parasitics and building a model used for statictiminganalysis). This resulted in two software products, NanGate Library Creator(TM)...
Global Information