Preesm information

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PREESM

PREESM 0.5.0 screenshot
Developer(s)	PREESM Development Team at IETR
Initial release	2008
Stable release	3.21.0[1]  / 1 October 2020; 3 years ago (1 October 2020)
Repository	github.com/preesm/preesm
Written in	Java as Eclipse plug-ins
Type	Rapid Prototyping Tool
License	CeCILL-B or CeCILL-C depending on the plug-ins
Website	preesm.org

PREESM (the Parallel and Real-time Embedded Executives Scheduling Method) is an open-source rapid prototyping and code generation tool. It is primarily employed to simulate signal processing applications and generate code for multi-core Digital Signal Processors. PREESM is developed at the Institute of Electronics and Telecommunications-Rennes (IETR) in collaboration with Texas Instruments France in Nice.

The PREESM tool inputs are an algorithm graph, an architecture graph, and a scenario which is a set of parameters and constraints that specify the conditions under which the deployment will run. The chosen type of algorithm graph is a hierarchical extension of Synchronous Dataflow (SDF) graphs named Interface-Based hierarchical Synchronous Dataflow (IBSDF). The architecture graph is named System-Level Architecture Model (S-LAM). From these inputs, PREESM maps and schedules automatically the code over the multiple processing elements and generates multi-core code.