Power integrity or PI is an analysis to check whether the desired voltage and current are met from source to destination. Today, power integrity plays a major role in the success and failure of new electronic products. There are several coupled aspects of PI: on the chip, in the chip package, on the circuit board, and in the system. Four main issues must be resolved to ensure power integrity at the printed circuit board level:[1]: 615
Keep the voltage ripple at the chips pads lower than the specification (e.g. less than ±50mV variation around 1V)
Control ground bounce (also called synchronous switching noise, simultaneous switching noise, or simultaneous switching output (SSN or SSO))
Control electromagnetic interference and maintain electromagnetic compatibility: the power distribution network is generally the largest set of conductors on the circuit board and therefore the largest (unwanted) antenna for emission and reception of noise.
Maintaining a proper DC voltage level at the load at high currents. A modern processor or field-programmable gate array can pull 1–100A from a sub-1V power rail with voltage margins in the tens of millivolts.[2][3] Very little DC voltage drop can thus be tolerated on the power distribution network.
^Cite error: The named reference Bogatin2009 was invoked but never defined (see the help page).
^"Simulating FPGA Power Integrity Using S-Parameter Models" (PDF). Xilinx. Retrieved 2018-03-18.
^"Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics" (PDF). Xilinx. Retrieved 2018-03-18.
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