A CVAX system card with the CVAX CPU on the right, the CFPA floating-point unit on the left, and the CVAX clock chip above the CFPA.
The CVAX is a microprocessor chipset developed and fabricated by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). The chipset consisted of the CVAX 78034 CPU, CFPA floating-point accelerator, CVAX clock chip, and the associated support chips, the CVAX System Support Chip (CSSC), CVAX Memory Controller (CMCTL), and CVAX Q-Bus Interface Chip (CQBIC).
the CVAX 78034 CPU, CFPA floating-point accelerator, CVAX clock chip, and the associated support chips, the CVAX System Support Chip (CSSC), CVAX Memory...
VAX processors followed in the form of the V-11, CVAX, CVAX SOC ("System On Chip", a single-chip CVAX), Rigel, Mariah and NVAX implementations. The VAX...
MicroVAX 3100 Model 10 Teammate II KA41-A, CVAX, 11.11 MHz (90 ns) MicroVAX 3100 Model 10e Teammate II KA41-D, CVAX+, 16.67 MHz (60 ns) 32 MB of memory maximum...
(60 ns) CVAX+ microprocessor with a 64KB external cache. Code named "PVAX", it used the KA42-A CPU module containing an 11.12 MHz (90 ns) CVAX microprocessor...
floating-point coprocessor, but later Firefly systems used the faster CVAX 78034 microprocessors, CVAX Floating Point Chips (floating-point coprocessors). The processor...
"Calypso" Introduced on 19 April 1988 One to four 12.5 MHz (80 ns cycle time) CVAX chip set(s), each with an external 256 KB of secondary cache built from 160...
University. Steal The Best, a micrograph of a Digital Equipment Corporation CVAX microprocessor used in the MicroVAX and VAX 6200 systems. It contains "VAX...
modifications. This became the "EVAX" concept, a follow-on to the successful CMOS CVAX implementation. When management accepted the findings, they decided to give...
with the image of the LSI-11 CPU in the User Manual. Which emerged as the CVAX. DEC codenames of the time referenced Greek deities and heroes, or were reminiscent...
It used the KA520 CPU module containing a 16.67 MHz (60 ns cycle time) CVAX+ chip set with 32 KB of external secondary cache. The system contained two...