Time delay between data read command and availability of data in a computer's RAM
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Column address strobe latency, also called CAS latency or CL, is the delay in clock cycles between the READ command and the moment data is available.[1][2] In asynchronous DRAM, the interval is specified in nanoseconds (absolute time).[3] In synchronous DRAM, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of absolute time, the actual time for an SDRAM module to respond to a CAS event might vary between uses of the same module if the clock rate differs.
^Stokes, Jon "Hannibal" (1998–2004). "Ars Technica RAM Guide Part II: Asynchronous and Synchronous DRAM". Ars Technica. Archived from the original on 2012-11-01.
^Jacob, Bruce L. (December 10, 2002), Synchronous DRAM Architectures, Organizations, and Alternative Technologies(PDF), University of Maryland
^Memory technology evolution: an overview of system memory technologies, HP, July 2008
Column address strobe latency, also called CASlatency or CL, is the delay in clock cycles between the READ command and the moment data is available. In...
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