The address generation unit (AGU), sometimes also called address computation unit (ACU),[1] is an execution unit inside central processing units (CPUs) that calculates addresses used by the CPU to access main memory. By having address calculations handled by separate circuitry that operates in parallel with the rest of the CPU, the number of CPU cycles required for executing various machine instructions can be reduced, bringing performance improvements.[2][3]
While performing various operations, CPUs need to calculate memory addresses required for fetching data from the memory; for example, in-memory positions of array elements must be calculated before the CPU can fetch the data from actual memory locations. Those address-generation calculations involve different integer arithmetic operations, such as addition, subtraction, modulo operations, or bit shifts. Often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarily decode and execute quickly. By incorporating an AGU into a CPU design, together with introducing specialized instructions that use the AGU, various address-generation calculations can be offloaded from the rest of the CPU, and can often be executed quickly in a single CPU cycle.[2][3]
Capabilities of an AGU depend on a particular CPU and its architecture. Thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multiple operands at a time.[2][3] Furthermore, some CPU architectures include multiple AGUs so more than one address-calculation operation can be executed simultaneously, bringing further performance improvements by capitalizing on the superscalar nature of advanced CPU designs. For example, Intel incorporates multiple AGUs into its Sandy Bridge and Haswell microarchitectures, which increase bandwidth of the CPU memory subsystem by allowing multiple memory-access instructions to be executed in parallel.[4][5][6]
^Cornelis Van Berkel; Patrick Meuwissen (January 12, 2006). "Address generation unit for a processor (US 2006010255 A1 patent application)". google.com. Retrieved December 8, 2014.
^ abc"Chapter 4: Address Generation Unit (DSP56300 Family Manual)" (PDF). ecee.colorado.edu. September 16, 1999. Archived from the original (PDF) on March 29, 2018. Retrieved December 8, 2014.
^ abcDarek Mihocka (December 27, 2000). "Pentium 4: Round 1 – Intel blows the lead". emulators.com. Retrieved December 8, 2014.
^David Kanter (November 13, 2012). "Intel's Haswell CPU Microarchitecture: Haswell Memory Hierarchy". realworldtech.com. Retrieved December 8, 2014.
^Per Hammarlund (August 2013). "Fourth-Generation Intel Core Processor, codenamed Haswell" (PDF). hotchips.org. p. 25. Archived from the original (PDF) on July 5, 2016. Retrieved December 8, 2014.
and 21 Related for: Address generation unit information
The addressgenerationunit (AGU), sometimes also called address computation unit (ACU), is an execution unit inside central processing units (CPUs) that...
improve performance. The addressgenerationunit (AGU), sometimes also called the address computation unit (ACU), is an execution unit inside the CPU that...
other internal units such as an arithmetic logic unit, addressgenerationunit, floating-point unit, load–store unit, branch execution unit or some smaller...
is different. The SCC68070 lacks a dedicated addressgenerationunit (AGU), so operations requiring address calculation run slower due to contention with...
actin-based). Adder (electronics) Addressgenerationunit (AGU) Load–store unit Binary multiplier Execution unit Atul P. Godse; Deepali A. Godse (2009)...
shift left, in cases where limited by a fixed amount (e.g. for addressgenerationunit). One way to implement a barrel shifter is as a sequence of multiplexers...
MCU may refer to: Address computation unit, another name for addressgenerationunit Automatic Client Upgrade, a facility within the Novell Open Enterprise...
cycle integer multiplication unit Branch prediction Dual instruction pipeline Instructions in the addressgenerationunit (AGU) and thereby supply the...
memory location. It can be called an address-translation cache. It is a part of the chip's memory-management unit (MMU). A TLB may reside between the CPU...
least-significant 64 bits of an address) can be independently self-configured by a host. The SLAAC addressgeneration method is implementation-dependent...
Gymnastics (FIG) Addressgenerationunit, a part of computer processors involved in performing memory accesses Anhydroglucose unit, a single sugar molecule...
The 68060 has the ability to execute simple instructions in the addressgenerationunit (AGU) and thereby supply the result two cycles before the ALU....
useful for calculating FFTs Exclusion of a memory management unitAddressgenerationunit In 1976, Richard Wiggins proposed the Speak & Spell concept to...
execution environment that are built into some Intel central processing units (CPUs). They allow user-level and operating system code to define protected...
Generation X (often shortened to Gen X) is the demographic cohort following the Baby Boomers and preceding Millennials. Researchers and popular media often...
An Internet Protocol version 6 address (IPv6 address) is a numeric label that is used to identify and locate a network interface of a computer or a network...
texture mapping units: render output units To calculate the processing power, see Performance. Full G80 contains 32 texture addressunits and 64 texture...
are the demographic cohort following the Silent Generation and preceding Generation X. The generation is often defined as people born from 1946 to 1964...